Zephyr And RISC-V: I Aint Afraid of No Ghosts (FOSDEM 24)

RISC-V's instruction set architecture (ISA) has enabled seasoned embedded software engineers to experiment with FPGAs since numerous open-source RISC-V cores can be flashed onto an FPGA. The Zephyr Project is rapidly emerging as a leading real-time operating system (RTOS). Zephyr integrates open-source and security best practices to ensure a vendor-neutral, secure, and reliable platform. In this talk, Mohammed Billoo will describe the process of getting to Zephyr to run on the UPduino (https://tinyvision.ai/pages/the-upduino), flashed with the neorv32 RISC-V processor (https://github.com/stnolting/neorv32). He will walk through building and flashing the neorv32 RISC-V core on the FPGA, creating a Zephyr application that can output Hello World to the UART, and loading the application to the FPGA. Mohammed will also walk through the necessary Zephyr drivers to get the application running. This talk will demonstrate how combining RISC-V and Zephyr on an FPGA opens up new opportunities for embedded software applications. Using open-source software and firmware on a low-cost FPGA reduces the bar for entry for enthusiasts and hobbyists. The audience will learn the following in this talk: Relevance of the RISC-V instruction set architecture for hobbyists Overview and structure of the neorv32 RISC-V processor Overview and structure of The Zephyr Project RTOS RISC-V support in Zephyr Relevant Zephyr drivers Demo: From Empty Silicon To Zephyr Boot