VERILATOR Introduction

This video covers an introduction to the free and open source SystemVerilog simulator Verilator. Verilator contains a variety of useful features and is competitive with the "Big 3" commercial tools. · · · References · · · • Featured GitHub Repo: https://github.com/sifferman/verilator_example • Verilator Repo: https://github.com/verilator/verilator • OSS CAD Suite: https://github.com/YosysHQ/oss-cad-suite-build • "Goodbye Make, Hello SiliconCompiler!": https://youtu.be/GM9PKAfTlmQ · · · Timestamps · · · 0:00 Intro 1:09 Installation 2:22 Basic Example 3:13 Verilation Explanation 3:55 Warnings 5:06 Disabling Warnings 5:46 Verilator Filelist 6:17 Favorite Verilator Arguments 6:56 4-State Values 7:53 UVM 8:03 Call to Action! 8:30 Outro