PCIe Active Electrical Cables AECs Enabling Scale Out Large Language Model LLM Computing Clus

"Chris Kapuscinski (Director- New Product Development) - Molex Chris Petersen (Fellow Of Technology And Ecosystems) - Astera Labs The move towards active electrical cables (AECs) utilizing retimers for 112G and 224G PAM4 ethernet applications has been driven by the desire to utilize lower cost copper-based solutions (compared to optical) while maintaining sufficient channel reach. The same retimer technology is being evaluated for compute PCIe applications. The desire to connect/cluster multiple GPUs / Accelerators within a rack (scale-up) and across racks (scale-out) to enable Large Language Models (LLM) is a driving factor for developing retimed PCIe AECs. But PCIe and Ethernet are different communication protocols and hence result in new challenges / considerations arise- including:\n· How best to enable retimers in CDFP- the official PCIe SIG form format?\n· What advantages/disadvantages do alternative form factors such as OSFP-XD offer? \n· How retimer implementation in PCIe applications differs from Ethernet?"