Presented by: Meta | Dheepak Jayaraman, ASIC Engineering Manager | U2U India 2025 |
The rise of RISC-V based AI accelerators has revolutionized the field of artificial intelligence, offering unparalleled flexibility and openness. However, as these systems grow in complexity and heterogeneity, debugging becomes a significant challenge.
In his presentation, Dheepak introduces the debug and SLT framework, a comprehensive and efficient solution designed to tackle the unique challenges of RISC-V based AI accelerators.
By providing a scalable and reliable approach to debugging, this framework empowers developers to unlock the full potential of these systems. Watch the full presentation to learn more.
Bio: Dheepak Jayaraman
Dheepak Jayaraman holds a PhD in Electrical and Computer Engineering from Southern Illinois University Carbondale and brings 2 decades of experience in the semiconductor industry. As an ASIC Engineering Manager at Meta, he leads the implementation team. Previously at Meta has also lead SoC design, CPU Subsystem, CPU trace architecture, advanced debug solutions, and scalable DFT methodologies. Throughout his career, he has made significant contributions to DFT, CPU trace, and debug, developing cutting-edge telemetry and debug systems that effectively address complex industry challenges.
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