Introducing HW Accelerated Velox with CXL Computational Memory = Harry Kim, XCENA

Introducing HW Accelerated Velox with CXL Computational Memory = Harry Kim, XCENA

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Introducing HW Accelerated Velox with CXL Computational Memory = Harry Kim, XCENA
Meeting the ever-increasing demands of data analytics requires more memory and larger computing clusters. However, scaling these infrastructures is complex, costly, and yields diminishing returns. CXL is an advanced interconnect technology that expands memory while maintaining cache coherency, enabling unprecedented memory-centric computing—unlike traditional PCIe-based hardware accelerators (e.g., GPUs). This session introduces XCENA’s CXL computing hardware and software stack and presents a roadmap for implementing Velox integration and Velox-Gluten-Spark applications. XCENA has a many-core parallel architecture optimized for big data processing and supports software development based on C++/Rust using a distributed framework similar to MapReduce. Additionally, through XFLARE, a query processing engine optimized for XCENA hardware, you can directly execute queries by connecting to the data analytics engines you primarily use, such as Velox, Presto or Spark(via Gluten). Link to slides: https://shorturl.at/RRGH2