DVD - Lecture 11: Sign Off and Chip Finishing - Part 1

Bar-Ilan University 83-612: Digital VLSI Design This is Lecture 11 of the Digital VLSI Design course at Bar-Ilan University. In this course, I cover the basics of Chip Implementation, from designing the logic (RTL) to providing a layout ready for fabrication (GDS). Lecture 11 wraps up the RTL to GDS flow with the extra steps that are needed to take a design that has finished place and route and prepare it for tape-out. Part 1 of the lecture focuses on the various margins and issues in sign-off timing, such as OCV, PBA, and Aging. Lecture slides can be found on the EnICS Labs web site at: https://enicslabs.com/academic-courses/dvd-english/ All rights reserved: Prof. Adam Teman Emerging nanoscaled Integrated Circuits and Systems (EnICS) Labs Faculty of Engineering, Bar-Ilan University